Which is Intel level of dubious fake market segmentation considering those are no longer Chipsets, but rather southbridges sitting away from main PCIE lanes and memory buses.
A possible plausible explanation is that AMD's SAM is "just" that they fixed the BAR size limits so the entire vram can be mapped at once, instead of the still weirdly common & low 256MB limit. If so, that would actually involve the chipset (even if it's just the supporting BIOS & microcode) and not just the CPU.
The software that runs the PCIE controller isn't on the CPU, though. And at least at launch only the 500 series chipsets support the Ryzen 5000 CPUs. Maybe this will come to the 400 series chipsets later that get Ryzen 5000 support, or maybe this is something that was cut to squeeze in Ryzen 5000 support for the 400 series chipsets.
